A non-volatile semiconductor memory may be employed as mass storage for a computer system (e.g., desktop, laptop, portable, etc.) or a consumer device (e.g., music player, cell phone, camera, etc.) or other suitable application. The non-volatile semiconductor memory may comprise one or more memory devices (such as a flash memory) and control circuitry for accessing each memory device. Each memory device is coupled to an I/O bus, as well as a number of interface control lines. When issuing a program command or an erase command to a memory device, the control circuitry transfers the address and command data (and write data for a program operation) over the I/O bus. When issuing a read command, the control circuitry transfers the address and command data over the I/O bus and then receives the read data over the I/O bus.
FIG. 1 shows a prior art non-volatile semiconductor memory 2 communicating with a host 4 according to a suitable communication protocol. A memory controller 6 comprises a buffer 8 for buffering data for write/read commands, and a microprocessor 10 executing control programs for various algorithms, such as a logical block address (LBA) to physical block address (PBA) mapping, wear leveling, error correction code, etc. The memory controller 6 further comprises interface circuitry 12 for interfacing with one or more memory devices 14, such as a suitable flash memory device. The interface circuitry 12 generates suitable control signals 16 and receives status information 18 from the memory device 14 in connection with executing write/read commands initiated by the microprocessor 10. The interface circuitry 12 also transmits and receives data over an I/O bus 20, including read/write data stored in the buffer 8 or command data generated by the microprocessor 10 and transmitted to a controller 22 integrated with the memory device 14.
The memory device 14 comprises an array of memory cells 24 that are accessed in memory segments referred to as pages. During a write operation, write data received over the I/O bus 20 from the buffer 8 is first stored in a data register 26. The controller 22 then transfers the write data from the data register 26 to a target page in the memory array 24. During a read operation, a page in the memory array 24 is read into the data register 26 and then transferred over the I/O bus 20 where it is stored in the buffer 8.
During a write operation, the memory device 14 will typically only flush the write data stored in the data register 26 to a page in the memory array 24 in response to a flush command received from the microprocessor 10 of the memory controller 6. For example, the write sequence for a typical flash memory is to issue a 30h command, followed by the address to store the data in the memory array 24, followed by a 10h command which instructs the controller 22 to transfer the write data stored in the data register 26 to the target page in the memory array 24. This implementation allows the memory controller to transmit partial pages of memory at a time before transmitting a flush command. For example, if the non-volatile semiconductor memory 2 implements a solid state drive (SSD), each data sector of the SSD may be less than the page size of the memory array 24 (e.g., 512 byte sector size and 2 k byte page size). The memory controller 6 may transmit a data sector at a time to the memory device 14 during “single sector” write operations, and after transmitting enough data sectors to fill a page, transmit a flush command (e.g., 10h) to flush the write data from the data register 26 to the target page in the memory array 24. However, if a power failure occurs after executing a number of single sector write operations but prior to issuing the flush command, the write data cached in the data register 26 may be lost.